About this course

Course code TPMSF3
Duration 2 Days

This is the third course in the definitive 'z/OS Fundamentals' series of courses. In today's multiple processor environments it is essential that Systems Programmers and Software Developers have a solid understanding of Locking, SVCs and the SSI, along with knowing how address spaces communicate.<br>This course describes and explains how locking works. It also describes how z/OS services are requested. When calling services within z/OS there are two basic interfaces available: Supervisor Calls (SVCs) and the Subsystem Interface (SSI). This course explores the underlying communication between Address Spaces. This encompasses the scheduling of SRBs before looking into Cross Memory Service (XMS). XMS is invoked using various machine instructions which are described in some detail, along with the relevant PSW and Control Register usage. The Architecture description is then completed by exploring Access Register Mode (AR) and how this is used in conjunction with Data Spaces.<br><br>This course is available 'on demand' (minimum 2 students) for public presentations or for one-company, on-site presentations.

Prerequisites

Attendees should have attended the courses z/OS System Fundamentals Part l and z/OS System Fundamentals Part 2 or equivalent experience. Some IPCS skills would also be useful. Knowledge of Assembler would also be extremely helpful, but is not mandatory.

Delegates will learn how to

  • understand how locking works
  • diagnose locking problems in an SVC dump
  • explain the significance of the different SVC types
  • write & implement User SVCs
  • describe how SSIs work
  • understand the responsibilities of the Subsystem modules
  • call SSI services
  • create and schedule SRBs
  • set up the environment for XMS Program Sharing
  • set up the environment for Data Sharing
  • understand how ART works
  • set up and exploit Dataspaces
  • set up and exploit Hiperspaces.

Outline

z/OS Architecture

The architectural principles of the CPU; PSW, registers; interrupts system states; PSW swapping; multi-processing; central storage; addressing modes; storage keys; parallel & serial channels; pathing; HCD; LCUs; CCWs; I/O operation; SCSW.

Interactive Problem Control System

Control block/data area; Information sources; Control block header; Control block data area map; Cross reference table; Fields and subfields; Field redefinitions; Control block chaining; Finding control blocks; The Prefix Area (PSA); The new Prefix Area (PSA); Dump types; IPCS introduction: what is IPCS?, What makes up IPCS?; Getting started with IPCS - Primary Option Menu; Default values selection; Primary Option Menu; Data entry panel; Pointer stack panel; Getting around in IPCS browse; IPCS subcommand entry panel; IPCS command output display; IPCS LIST command; Indirect addressing; Displaying Control Blocks; Creating SYMBOLS: Dump Directory; Additional Useful Commands; Dump analysis panel; Component Data Analysis Panel; STATUS; Analysis commands; Dump Management panel.

System Locks

What are System Locks; Compare and Swap instruction; Lock Manager; Spin Locks; Suspend Locks; Spin Lock processing; Excessive spin loops; Spin Lock recovery; Suspend Lock processing; Lockword locations; Lockword status; Diagnosing Locking problems in an SVC dump.

Supervisor Calls (SVCs)

SVC request options; Supervisor call services; SVC processing; SVC FLIH, Exit prologue; SVC interrupt; SVC table; SVC types and attributes; ESR SVCs; User SVCs; Setting up an SVC; Find and analyse SVC Table entries.

Subsystem Interface (SSI)

Examples of SSIs; Identifying the service; Subsystem name; Function id; Master Subsystem; Establishing a subsystem; Defining a subsystem; Subsystem control blocks; Requesting a subsystem service; SSIB and SSOB control blocks.

Inter Address Space Communication

Address Space communication; A Service Request; SRB control block; SRB types and priorities; IEAMSCHD; Work Unit Queue (WUQ); Service request examples; SRB overhead; Cross Memory Services; Program sharing; Data Sharing; Linkage and Entry tables; Address Space First and Second tables; Authorization tables; Progam Call (PC) and Program Transfer (PT); LXRES, ETDEF & ETCRE macros; PC number translation; Extended ETE; Stacking PCs; Linkage Stack; PC authorization; PT Authorization; SSAR & MVCP instructions.

Dataspaces and Hiperspaces

Access Register Translation; Access List; Locating Access Lists; Extended ASN Second-Table-Entry; ALETs; ART authorization 'Invalid ALEN', 'Invalid ALESN', 'Any Requestor, 'Private Indicator'; ART Lookaside buffer; Access Register instructions; Creating Data Spaces; DSPSERV macro; Dispatchable Unit Address List (DUAL); Primary ASN Access List (PASN-AL); ALESERV macro; Using the new Dataspace; Creating a Hiperspace; HSPSERV & IOSADMF macros; Types of Hiperspaces; DSPSERV macro; Accessing a Hiperspace; Subspace Group Facility (SGF); SGF hardware; DUCT & BSG instruction.

2 Days

Duration
Delivery Method

Delivery method

Classroom

Face-to-face learning in the comfort of our quality nationwide centres, with free refreshments and Wi-Fi.

Find dates and prices

Online booking is currently not available for this course, to find out more please call us on 0345 074 7998 or email us at info@qa.com to discuss how we can help.

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